The University of Sydney, University of NSW and Perceptia Devices Australia will offer an exciting opportunity in advanced, high speed circuit design to only two of the most qualified PhD candidates. These very select positions will offer a rare opportunity to gain real world experience, working along side industry professionals, on some of the worlds most advanced circuits. Your participation ensures you of a quality dissertation topic where you'll pioneer new circuit designs on advanced process geometries available to only the worlds most technically advanced semiconductor companies. This experience will prepare you for global semiconductor opportunities in the world's most prestigious semiconductor companies.
Please pass this along if you know someone who is interested.
This project will develop circuits to meet the challenges of high speed circuit design in the latest IC manufacturing technologies. Using the latest in design tools and methodologies, you will be developing new circuit topologies to achieve maximum performance from the most advanced process currently in production and the next few generations, yet to be released. These processes have extremely small transistors that offer very high speed and bandwidths at the cost of operating off a very low supply voltage. Success here will require innovative new techniques and concepts that will require bold new ideas and exploration. New ideas that will come from you. Are you ready? Are you capable? Are you up for the challenge?
There are two main challenges that can be addressed as part of this research:
Ultra high speed logic:
Conventional CMOS logic circuits can be operated at up to 15GHz in a 40nm process. However certain applications demand logic blocks operating in excess of 30GHz. Traditionally CML logic has been used in this role, but the low swing possible means that it is not attractive in these technologies. You will be investigating circuit topologies to achieve the fastest logic operations, probably trading increased power dissipation for logic speed.
Alternate analog structures:
The high ratio of threshold voltage to power supply used in modern CMOS process means that many traditional analog circuit topologies can no longer be used. For example there is insufficient headroom to use a cascaded differential amplifier. Matching and linearity are also worse than in older technologies. You will be investigating circuit topologies able to provide amplification and filtering given these limitations and taking advantage of the increased bandwidth offered by these technologies.
This project is supported by an ARC linkage grant and Perceptia Devices Australia. In addition to being paid a APAI scholarship, you will be have the opportunity to work with Pereptia's engineering team in the real engineering world. You will also also have access through Perceptia to manufacturing technologies far more advanced than available to any other academic project in Australia.
This project may include opportunities to travel to California to work with Perceptia's Silicon Valley team when characterising your circuits.
Candidates must be suitably qualified students with Australian nationality or permanent residency or the ability to pay all university fees. Assistance to move to Sydney is available.
If you are interested in applying, please contact:
Julian: julian@perceptia.com
Andre: andre.vanschaik@sydney.edu.au
or
Tara: t.hamilton@unsw.edu.au
Applications close 12/7/2010
Please pass this along if you know someone who is interested.
This project will develop circuits to meet the challenges of high speed circuit design in the latest IC manufacturing technologies. Using the latest in design tools and methodologies, you will be developing new circuit topologies to achieve maximum performance from the most advanced process currently in production and the next few generations, yet to be released. These processes have extremely small transistors that offer very high speed and bandwidths at the cost of operating off a very low supply voltage. Success here will require innovative new techniques and concepts that will require bold new ideas and exploration. New ideas that will come from you. Are you ready? Are you capable? Are you up for the challenge?
There are two main challenges that can be addressed as part of this research:
Ultra high speed logic:
Conventional CMOS logic circuits can be operated at up to 15GHz in a 40nm process. However certain applications demand logic blocks operating in excess of 30GHz. Traditionally CML logic has been used in this role, but the low swing possible means that it is not attractive in these technologies. You will be investigating circuit topologies to achieve the fastest logic operations, probably trading increased power dissipation for logic speed.
Alternate analog structures:
The high ratio of threshold voltage to power supply used in modern CMOS process means that many traditional analog circuit topologies can no longer be used. For example there is insufficient headroom to use a cascaded differential amplifier. Matching and linearity are also worse than in older technologies. You will be investigating circuit topologies able to provide amplification and filtering given these limitations and taking advantage of the increased bandwidth offered by these technologies.
This project is supported by an ARC linkage grant and Perceptia Devices Australia. In addition to being paid a APAI scholarship, you will be have the opportunity to work with Pereptia's engineering team in the real engineering world. You will also also have access through Perceptia to manufacturing technologies far more advanced than available to any other academic project in Australia.
This project may include opportunities to travel to California to work with Perceptia's Silicon Valley team when characterising your circuits.
Candidates must be suitably qualified students with Australian nationality or permanent residency or the ability to pay all university fees. Assistance to move to Sydney is available.
If you are interested in applying, please contact:
Julian: julian@perceptia.com
Andre: andre.vanschaik@sydney.edu.au
or
Tara: t.hamilton@unsw.edu.au
Applications close 12/7/2010